The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. Because of its lower bulk resistivity, Copper (Cu) is commonly employed as the conducting layer material. Often, a damascene or dual damascene process is used to provide Cu metallization. The copper is deposited within the damascene opening and polished back to form “plugs” within the contact/via opening. Then, a capping layer, such as silicon nitride or silicon carbide, is deposited over the copper plugs to prevent copper from diffusing into overlying layers.
During the deposition of the capping layer, a compressive-thermal stress may be induced on the copper, causing a vertical strain on the copper surface. FIG. 1A illustrates a copper damascene line 120 within an insulating layer 118 on a semiconductor substrate 110. Copper oxide 122 has formed naturally on the surface of the copper after planarization. FIG. 1B shows the compressive-thermal stress 130 acting along grain boundaries within the copper during deposition of the capping layer 140. FIG. 1C shows copper hillocks 132 formed by the vertical thermal strain on the copper surface. Copper hillocks reduce copper reliability and cause via induced metal island corrosion (VIMIC), and confuse defect inspection tools so that other defects cannot be detected accurately.
In the production process of integrated circuits, devices are tested to estimate the device yields and possible yield-detracting processing problems. Since the production of integrated circuits includes many processing steps and different technologies, the technological sources of electrical failure such as short circuits within the integrated circuits or open contacts are investigated using test structures in order to estimate a suitable process window and to improve the device quality as well as the processing yield. It is known that copper hillocks may confuse defect inspection tools so that other defects cannot be detected accurately. The detection of copper hillocks is thus desirable to better monitor the performance of the production process and to provide a better estimate of a suitable process window.
Accordingly, it is desirable to provide improved integrated circuits with copper hillock detection features that are robust and able to detect the presence of copper hillocks through the various defects that they induce. Additionally, it is desirable to provide such integrated circuits that are compatible with existing fabrication technologies. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.